EL2242辅导、辅导C/C++程序语言
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State Machines also called finite state machines are a method of modelling a system that at its basis describes
the behavior of a system and how it is contained into set states with each state being a distinct part of the overall
model. Actions that allow the movement of a system between states are called transitions. A simple state
machines is a turnstile and is described below:
Figure 1 – Turnstile described as a state machine
Image taken from - https://en.wikipedia.org/wiki/Finite-state_machine
As can be seen in figure 1 the turnstile has 2 states, locked and unlocked, with 2 actions that are allowed (coin
inserted and the user pushing the turnstile). The entry to the system is the “locked” state. If a user was to “push”
the state remains the same (Locked). When a coin is inserted the state is changed to unlocked. If the user
pushes this turnstile (to move through it) the state changes back to Locked. If in the unlocked state another coin
is inserted then the machine stays in the unlocked state.
The state machine diagram shown in figure 1 describes the above paragraph in an easy to understand concept
that allows the implementation of this logical system in a number of ways.
You are required to develop a simple finite state machine using the C programming language + ARM
microcontroller and Using Verilog HDL in the Quartus development environment. The state machine will mimic
the operation of a 2 stage security gate.
The security gate works with the following operation.
1. A security card is presented to a scanner
2. The card is verified/rejected
3. If the card is verified a fingerprint is taken
4. The fingerprint is verified/rejected
5. If the fingerprint and the card is verified the gate will open
Define the state machine by using an appropriate diagram, ensuring that all states and transitions are
documented.
Implement the state machine using two different technologies:
i) ARM STM32XXXXXX microcontroller using the C language
ii) Verilog HDL using Quartus
Both implementations should use appropriate input methods to denote the card/fingerprint and appropriate
output method(s) to denote gate being locked/unlocked (switches/buttons for inputs, LED’s etc for outputs).
In each case, ensure that the system operates correctly, and record your results and test this against a set of
testing criteria determined by yourself. As part of the development process you should also run a simulation or
debugging where appropriate.
Include simulation results of the Verilog code to show the system working where you do not have a development
board available.
In addition to the working code you are require to write a report, this is outlined below.
Development Report
You are tasked with creating a technical report of the development of the system. Within the report ensure that
you cover the following aspects:
Researched background into state machines and their development
Comparisons between Microcontrollers and FPGA technology and how they work
System design and implementation
State machine diagrams for the system implemented
System testing
Results (including s
State Machines also called finite state machines are a method of modelling a system that at its basis describes
the behavior of a system and how it is contained into set states with each state being a distinct part of the overall
model. Actions that allow the movement of a system between states are called transitions. A simple state
machines is a turnstile and is described below:
Figure 1 – Turnstile described as a state machine
Image taken from - https://en.wikipedia.org/wiki/Finite-state_machine
As can be seen in figure 1 the turnstile has 2 states, locked and unlocked, with 2 actions that are allowed (coin
inserted and the user pushing the turnstile). The entry to the system is the “locked” state. If a user was to “push”
the state remains the same (Locked). When a coin is inserted the state is changed to unlocked. If the user
pushes this turnstile (to move through it) the state changes back to Locked. If in the unlocked state another coin
is inserted then the machine stays in the unlocked state.
The state machine diagram shown in figure 1 describes the above paragraph in an easy to understand concept
that allows the implementation of this logical system in a number of ways.
You are required to develop a simple finite state machine using the C programming language + ARM
microcontroller and Using Verilog HDL in the Quartus development environment. The state machine will mimic
the operation of a 2 stage security gate.
The security gate works with the following operation.
1. A security card is presented to a scanner
2. The card is verified/rejected
3. If the card is verified a fingerprint is taken
4. The fingerprint is verified/rejected
5. If the fingerprint and the card is verified the gate will open
Define the state machine by using an appropriate diagram, ensuring that all states and transitions are
documented.
Implement the state machine using two different technologies:
i) ARM STM32XXXXXX microcontroller using the C language
ii) Verilog HDL using Quartus
Both implementations should use appropriate input methods to denote the card/fingerprint and appropriate
output method(s) to denote gate being locked/unlocked (switches/buttons for inputs, LED’s etc for outputs).
In each case, ensure that the system operates correctly, and record your results and test this against a set of
testing criteria determined by yourself. As part of the development process you should also run a simulation or
debugging where appropriate.
Include simulation results of the Verilog code to show the system working where you do not have a development
board available.
In addition to the working code you are require to write a report, this is outlined below.
Development Report
You are tasked with creating a technical report of the development of the system. Within the report ensure that
you cover the following aspects:
Researched background into state machines and their development
Comparisons between Microcontrollers and FPGA technology and how they work
System design and implementation
State machine diagrams for the system implemented
System testing
Results (including s