代写EECS 31L: Introduction to Digital Logic Laboratory (Spring 2025) Lab 1代做Processing

EECS 31L: Introduction to Digital Logic Laboratory (Spring 2025)

Lab 1: Logic Block Design

This is a very brief lab report template. It provides a possible outline for your report. Your lab report should clearly explain your design and testing results – readers of your report should be able to reproduce your design solely by reading your report.

NOTE: Please refer to each lab manual for detailed instructions on what to include in your report. You will lose points if you do not include all the required content.

1    Overview

Give a summary or a high-level overview of the design.  Use a block diagram for your design to explain inputs, outputs and the relation between them. If your design has more than one module, explain how they are related.

2    Hardware Design

In this section describe how you design your hardware modules. If necessary, you may show some Verilog code samples. A truth table helps to find the boolean equation (if you want to use logical operators), or in general the relation between inputs and outputs. For more complex designs you can also draw the schematic of your design. The schematic of design includes the components of the design and their connectivity. You can use any software like PowerPoint to draw your figures.

3    Simulation Results

Show your simulation results here.  Explain your test cases and how you design them to cover all combi- nations of inputs.  Put screenshots of your simulation here.  You may need to put more than one image if necessary.  Also, define the signals in the screenshots and explain how and when the input changes cause changes in the output. If there is something different from what you expect, explain why.