代做Computer Systems Architecture 2023/24 Cache controller simulator Part 2代做Python程序

Computer Systems Architecture 2023/24

Laboratory Exercise - Cache controller simulator Part 2

1.   Introduction

The Computer Systems Architecture laboratory exercise has two parts. In the first part you have written and validated a C program to simulate the operation of a direct mapped cache controller on an embedded processor. In the second part, you will use your simulator to analyse the impact of cache memory size and cache memory block size on the performance of the embedded system sorting an array of integer values using abubble sort algorithm.

You will work individually on this laboratory exercise; submitting a C program, a memory trace file used for validation and a short report.

2.   Embedded system memory architecture

The embedded processor is interfaced to a 256 Ki x 16-bit external data memory using a 20-bit address bus and a 16-bit data bus. The embedded processor contains a direct mapped cache controller for data accesses. The cache controller can be configured for cache sizes between 4 and 256 blocks and for cache block sizes between 2 and 32 16-bit words. The cache controller implements a Write-Allocate / Write-Back write policy.

3.   Bubble Sort Algorithm

You are provided with a memory trace file, bubble_sort_trace_nnn.txt, that contains the   values of the CPU address and data buses for each read and write access made by the CPU when sorting an array of random 16-bit integer values using a bubblesort algorithm.

Each student has their own unique trace file to analyse. You can find the value of the 3-digit ID number nnn identifying your unique trace file in the TRACE FILE ID column in Blackboard Gradebook.

The trace files can all be found in Dropbox folder https://tinyurl.com/2ynjb3wv

4.   Performance Analysis

Using your cache controller simulator and your own unique trace file, analyse the impact of cache memory size and cache memory block size on the performance of the embedded system when executing the bubblesort algorithm.

You should report a range of cache performance metrics as presented in the lecture materials. You are strongly encouraged to calculate program execution times and determine actual program speedup factors using the ‘no cache’ scenario as the performance baseline. You can assume that the main memory has access time of 100 ns, and the cache memory has an access time of 10 ns.

When analysing / explaining the results you will need to refer to the pattern of memory accesses when executing the bubblesort algorithm on the embedded processor. The implementation of the bubblesort algorithm executing on the CPU is presented in Appendix A. The memory trace file only records memory access to the array datavals[]. All other variables arestored in processor registers.

When presenting your analysis, include all relevant equations and clearly state all assumptions that have been made.

5.   Assessment

There is one element to the assessment of the second part of the laboratory exercise, a 4-page report. It contributes 10% towards the overall unit mark.

5.1. Cache Controller Performance Report

You are required to write a short report presenting the performance results from the cache controller simulations together with your analysis of these results. The report must present the performance results in both tabular and graphical formats. There is no requirement to discuss  method or background material.

The formatting requirements of the PDF document are described below. The font size requirement applies to all text in the document, including tables and graphs.

•    Paper size:         A4

•    Margins:             no smaller than 2cm

•    Font:                   Aptos, Arial, Calibri or Verdana with the font size no smaller than 11pt

•    Line spacing:      no less than 1.0

•    Length:               no more than 4 A4 sides

The report must include your name and your student ID number. There is no requirement for a title page. All tables must be presented as text, not animage. The report must be submitted as a PDF document (via Turnitin) to Blackboard.

The criteria for the assessment of the report, together with indicative percentage marks, are given below:

•   Appropriate selection of simulation parameters                     20%

•   Clarity of results presentation (tabular and graphical)            20%

•   Analysis of performance results                                           60%

5.2. Submission Deadline

The submission deadline for the Cache Controller Performance Report is 1 pm on Monday 29 April 2024. Automatic DASS extensions are available for this deadline.

Peter R Green

Version 1.0   5th  March 2024.

Appendix A - Source code for Bubble Sort Algorithm

/*

* Filename:     BubbleSort.c

* Author:        Jack Andrews

* Student ID:    123456789

* Date:         20 February 2019

*

*/

void BubbleSort(short int *datavals, int length) {

// Temporary variable used for swapping of elements

short int temp;

// Loop counters

int i, j;

/* Pass over the whole array on the first iteration. On subsequent

* iterations, ignore the already sorted upper elements, achieved by

* decrementing i on each iteration of the outer for() loop. */

for (i = length-1; i >= 0; i--) {

/* The inner for() loop iterates over the remaining array elements, * comparing each and swapping if necessary.

*/

for (j = 0; j < i; j++) {

/* Compare the value at index j in the array with the value at * index j+1. If datavals[j] > datavals[j+1], then swap the

* elements. */

if (datavals[j] > datavals[j+1]) {

// Swap the array elements

temp = datavals[j];

datavals[j] = datavals[j+1];

datavals[j+1] = temp;

}

}