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Course Code: BBU4202 Electronic Engineering Department
Lab Sheet 2: Logic Design using VHDL Date: ___________________________
Student’s Surname, First Name (in English):
____________________________________________ Student’s BUPT Number, Class Number: ________________________________
Email Username (ee11bxxx):
____________________________________________ Total Mark (out of 50):
________________________________
IMPORTANT:
(a)In advance of the lab session: Print this Lab Sheet, read it and complete all the indicated “Preparatory Work”.
(b)Write all your answers on this Lab Sheet, where indicated.
(c)Use additional A4 sheets of paper if you require more space to write your answers, ensuring that the question numbers are indicated clearly.
(d)Before handing in your Lab Sheet, make sure that you fill in the Table above with your personal details, and staple any additional answer sheets (with your name written on them) together with this Lab Sheet.
1.Learning Objectives & Preparatory Work
The aims of this Lab Session are to learn how to use VHDL to design and simulate some basic logic circuits, namely: a NAND gate and three types of Adders (Half, Full and Parallel).
2.VHDL Experiments
2.1. Create the Combinational Circuits
Using VHDL， design an 8-3 Priority Encoder/3-8 Decoder/8-1 Multiplexer. （Choose 1）
VHDL code
Write below the VHDL code!
2.2. Create the Test Bench and give simulation
2.3. Create the Sequential Circuits
Using VHDL， design an Modulo-10 Counter with synchronous set&load enable.
VHDL code
Write below the VHDL code
2.4. Create the Test Bench and give simulation
Course Code: BBU4202 Electronic Engineering Department
Lab Sheet 2: Logic Design using VHDL Date: ___________________________
Student’s Surname, First Name (in English):
____________________________________________ Student’s BUPT Number, Class Number: ________________________________
Email Username (ee11bxxx):
____________________________________________ Total Mark (out of 50):
________________________________
IMPORTANT:
(a)In advance of the lab session: Print this Lab Sheet, read it and complete all the indicated “Preparatory Work”.
(b)Write all your answers on this Lab Sheet, where indicated.
(c)Use additional A4 sheets of paper if you require more space to write your answers, ensuring that the question numbers are indicated clearly.
(d)Before handing in your Lab Sheet, make sure that you fill in the Table above with your personal details, and staple any additional answer sheets (with your name written on them) together with this Lab Sheet.
1.Learning Objectives & Preparatory Work
The aims of this Lab Session are to learn how to use VHDL to design and simulate some basic logic circuits, namely: a NAND gate and three types of Adders (Half, Full and Parallel).
2.VHDL Experiments
2.1. Create the Combinational Circuits
Using VHDL， design an 8-3 Priority Encoder/3-8 Decoder/8-1 Multiplexer. （Choose 1）
VHDL code
Write below the VHDL code!
2.2. Create the Test Bench and give simulation
2.3. Create the Sequential Circuits
Using VHDL， design an Modulo-10 Counter with synchronous set&load enable.
VHDL code
Write below the VHDL code
2.4. Create the Test Bench and give simulation