代做EECS 370 Winter 2023: Introduction to Computer Organization调试R语言程序

EECS 370 Winter 2023: Introduction to Computer Organization

1. Multiple choice           [15 pts]

Completely fill in the circle of the best answer.

1. Under what conditions would you expect a write-through cache to have a lower number of bytes transferred between the cache and memory than a write-back cache? [2]

The program has low spatial locality but high temporal locality

The program has high spatial locality but low temporal locality

The program has high spatial locality and high temporal locality

The program has low spatial locality and low temporal locality

Never

2. Functions are surprisingly difficult for the branch predictors we’ve discussed to deal with. What is it about functions that typically cause problems for those predictors? [2]

It is often hard to predict the “direction” of a function call.

It is often hard to predict the “direction” of the return from a function.

It is often hard to predict the target of the return from a function.

It is often hard to predict the target of a function call.

The branches associated with function calls and returns have very little spatial locality.

3. Which of the following formulas is equivalent to the circuit below? [2]

Q = A nor B

Q = A and B

Q = A or B

Q= not(A) or not(B)

None of the above

4. When comparing direct-mapped caches to fully-associative caches that otherwise have identical parameters, which of the following would be expected to be true? [3]

a) Direct-mapped caches will have a lower hit latency, fully-associative caches will have a higher hit rate

b) Direct-mapped caches will require more index bits, fully-associative caches will have more tag bits.

c) Direct-mapped caches will require fewer block offset bits, fully-associative caches will have more LRU bits.

Only a

Only b

Only c

Only a and b

Only b and c

Only a and c

All of a, b, and c.

For the next two questions, assume you have a byte-addressable, 256-byte virtually addressed cache with 16-byte blocks. Assume all entries in the cache start as “invalid” and addresses are 16-bits. All loads and stores are to 4-byte values.

5. For which of the following access patterns will a direct-mapped cache will get a better hit-rate than a two-way associative cache using LRU replacement? [3]

0x0000, 0x0010, 0x0020, 0x0000

0x0000, 0x0080, 0x0080, 0x0001

0x0000, 0x0180, 0x0080, 0x0000

0x0000, 0x0060, 0x0080, 0x0001

None of the above

6. For which of the following access patterns will a fully-associative cache using LRU replacement will get a better hit-rate than a two-way associative cache? [3]

0x0000, 0x0100, 0x0200, 0x0000

0x0000, 0x0001, 0x0200, 0x0002

0x0000, 0x0010, 0x0020, 0x0000

0x0000, 0x0410, 0x0020, 0x0000

None of the above

2. True or False               [13 pts]

Complete the following true or false questions.

(1) A clock with a 2ns period has a frequency of 200MHz.

True

False

(2) The number of LRU bits required for a set associative cache depends on cache associativity.

True

False

(3) An XOR gate can be created using only AND gates.

True

False

(4) A multi-level page table can take up more memory space than a single level page table.

True

False

(5) In the 3C’s cache model, a “compulsory” cache miss can sometimes be avoided by changing the cache’s total size while holding block size constant.

True

False

(6) A virtually-addressed cache doesn't need to access the TLB to see if the cache will get a hit or a miss.

True

False

(7) Virtual address space is generally limited to the amount of DRAM on a computer.

True

False

(8) Dennard scaling is the claim that each transistor will generally use the same amount of power no matter how small the transistor is.

True

False

(9) The size of a virtual page can be larger than the physical page.

True

False

(10) A 2-bit branch predictor can get about a 0% hit rate on a branch that alternates between taken and not-taken forever (so T, N, T, N, T, N...)

True

False

(11) In the 3 C’s model, you would expect to be able to reduce the number of conflict misses by increasing the associativity of the cache.

True

False

(12)Tags in TLBs are derived from virtual page numbers.

True

False

(13)If you increase the page size while holding DRAM’s size constant, you would expect the number of physical pages to increase.

True

False